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TM-250 External Signals

TM-250 Miniature CCD Camera

4 TM-250 External Signals

This section explains how the external signals (VD and HD) and shutter trigger signal (VINIT or TRIG)

must be fed in Async Mode operation, Integration Mode operation, and Reset-Restart operation.

4.1 External VD

The TM-250 I/F circuit intentionally delays the external VD for two pixel clock period. This ensures

that the phase of external HD comes earlier than that of VD with any cable length and absorbs the effect

of jitter caused by the user's sync generators. Assuming that the device propagation delay is more than

zero nanoseconds and the external VD timing is created by the edge of external HD, the HD must come

earlier than VD. Some sync generators, however, produce both VD and HD exactly in phase. In this

case, external factors like jitter or parasitic cable effects may cause VD to come earlier than HD as

shown in Figure 5 below.

FIGURE 5. External VD

4.2 External HD and Internal Sampling Clock

To ensure stable operation without inﬂuence of jitter, the TM-250 latches Shutter Trigger Pulse (TRIG)

using internal sampling clock called HCLK (half line clock). The frequency of HCLK is double of the

external HD and two pixels earlier than external HD in terms of timing. Figure 6 below shows that the

TRIG is latched in 1/2 line later for this reason.

FIGURE 6. Proper Operation

EXT HD

EXT VD (R.R.)

Internal VD

Two-pixel delay

Two pixels earlier

TRIG detected

Sample SampleSample

EXT HD

HCLK

TRIG

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Pulnix TM-250 Manual de instrucciones Pagina 22